The power of Vedic Mathematics can be explored to implement high performance multiplier in VLSI applications. Nikhilam Sutra in Vedic Mathematics is less complex than conventional multipliers, which can be tested with its implementation with different logics in VLSI. The proposed Vedic multiplier proves to be highly efficient in terms of speed. Due to its regular and parallel structure it can be realized easily on silicon as well. Regularity is a prominent feature of vedic mathematics which becomes vital in the implementation of circuit designs. The main advantage is delay increases slowly as input bits increase. VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing the algorithm.
Note:Microsoft Internet Explorer restricts the images to be uploaded one by one. To upload multiple images at the same time please use other browser.